[Solved]Compile: Freecad Pyside2 error on Debian

[petit_chat_noir]

Hello, just for information
After updating my Debian OS testing/unstable, I've found that cmake try to search Pyside2 in "/usr/lib/include/Pyside2", it's a bug in shiboken or pyside packaging I think.
what i did to make it working(uggly i know):
You have to copy /usr/include/Pyside2 folder to /usr/lib/include/Pyside2 and that's all

[reox]

I noticed the same and opened a bugreport in debian. The problem should be fixed in pyside2 from experimental.
But due to the transition to python3.8, it might take a while until it comes to testing.

[kkremitzki]

I uploaded it to experimental because there was a problem with compiling FreeCAD with that version, so if you feel brave feel free to try it. If you can confirm FreeCAD works with it then I can upload PySide 2 to unstable and begin its migration to testing.

[reox]

I had a build running against experimental, and the build itself seems to have worked.
But when I try to install it on my machine I get some errors regarading missing libpc-*1.9 - seems like I build against a wrong version, as the current version in testing is 1.10.
I'll try to restart the experimental build now.

[reox]

So one problem is that libshiboken 5.14 does not automatically remove 5.13:

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Unpacking libshiboken2-py3-5.14 (5.14.0-1~exp1) ...
dpkg: error processing archive /tmp/apt-dpkg-install-3JhUiK/0-libshiboken2-py3-5.14_5.14.0-1~exp1_amd64.deb (--unpack):
 trying to overwrite '/usr/lib/python3/dist-packages/shiboken2/__init__.py', which is also in package libshiboken2-py3-5.13 5.13.2-2.2+b1
dpkg-deb: error: paste subprocess was killed by signal (Broken pipe)

It can be solved though by removing 5.13 manually first.

However, it looks fine:

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OS: Debian GNU/Linux bullseye/sid (i3/i3)
Word size of OS: 64-bit
Word size of FreeCAD: 64-bit
Version: 0.19.19520 (Git)
Build type: Release
Branch: master
Hash: c01c1f7fde6851219d4b5ed38d906024be58e890
Python version: 3.8.1
Qt version: 5.12.5
Coin version: 4.0.0
OCC version: 7.3.0
Locale: German/Austria (de_AT)

Is there anything specific I can test to check if it works?

What I see is, that netgen seems to work less and less. Now I get segfaults when switching into FEM workbench even:

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/usr/lib/freecad-daily/lib/libNETGENPlugin.so: undefined symbol: _ZTVN6netgen11NgExceptionE
Traceback (most recent call last):
  File "<string>", line 46, in Initialize

Program received signal SIGSEGV, Segmentation fault.

But yeah, netgen seems to be another issue

edit: removed Netgen from build, and I can now open FEM workbench too.

[kkremitzki]

The problem I was running into was that the files generated by the new uic/rcc binaries was bad, particularly Mod/Draft/Draft_rc.py, and thus Draft WB and its dependents were broken.

[reox]

I usually not work with draft, but i created some shapes and it seems to work... But I'm not sure if this is what you asked for

[f3nix]

The problem I was running into was that the files generated by the new uic/rcc binaries was bad, particularly Mod/Draft/Draft_rc.py, and thus Draft WB and its dependents were broken.

Hi Kurt!
I've just compiled the version from experimental but I see the pyside2-tools are missing uic and rcc. Are you using the old tools?

I thought that we have to wait for Qt 5.14 in unstable to gain the ability to generate resources. https://bugreports.qt.io/browse/PYSIDE-1098

EDIT: Draft works using the old pyside2-tools and after installing new pyside2-qtsvg

Cheers,
Mateusz

[reox]

as far as I can tell from the changelog, the -uic package was removed, because it was merged into something else?

[kkremitzki]

pyside2-uic and pyside2-rcc and now just uic and rcc, and you have to add a flag to get the previous Python generation behavior.