Using named constraint in another constraint in the same sketch

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drmacro
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Using named constraint in another constraint in the same sketch

Post by drmacro »

Shown below is a named reference dimension (Constrant7, named tmax) and a non-reference dimension (Constraint6) in the same sketch.
(Note Constraint7/tmax is a reference dimension because the vertices it is measuring are in the external (shapebinder).
RefDim.png
RefDim.png (100.37 KiB) Viewed 1149 times
If I attempt to use tmax in an expression in Constraint6 :
CantUse.png
CantUse.png (130.37 KiB) Viewed 1149 times
But, Constraint6 needs to be some percentage of tmax (that percentage will ultimately come from a spreadsheet).
So an expression like this is the goal:

Code: Select all

tmax * Spreadsheet.somepercent
The scale of clone Wire001 will change the magnitude of tmax (because the shapebinder will change with Wire001)
(that scale will ultimately come form the spreadsheet as well.)

So, the question is how to access the distance between those particular vertices.
Attachments
test-2-2.FCStd
(17.82 KiB) Downloaded 15 times
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DeepSOIC
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Re: Using named constraint in another constraint in the same sketch

Post by DeepSOIC »

a) put the reference constraint into a separate sketch.
OR
b) refer to an existing edge somehow, if you have one, like =object_name.Shape.Edge35.Length * whatever

Using blue constraints to drive red constraints is not supported yet (both are calculated by solver, and solver constraints with internal expression support are not implemented yet).
drmacro
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Re: Using named constraint in another constraint in the same sketch

Post by drmacro »

DeepSOIC wrote: Sun Aug 09, 2020 6:52 pm a) put the reference constraint into a separate sketch.
OR
b) refer to an existing edge somehow, if you have one, like =object_name.Shape.Edge35.Length * whatever
See below...
Using blue constraints to drive red constraints is not supported yet (both are calculated by solver, and solver constraints with internal expression support are not implemented yet).
Noted.


I've tried a couple different ways with putting the reference dimension in another sketch. And I can get the things to scale fine.

For instance, as in this file I used a shapebinder in a body and then a sketch to reference vertices on the binder.

But, then when I use them with Curved Shapes make array I get an out of scope error (I don't think CS arrays like objects from a body...). :?:

And the point of the exercise is to make wing shapes.

I did try to draw a line between the points on the Wire001 but I don't know how to make it scale with the Wire001. (That avoids using the shapebinder that needs to be in a body. So that would eliminate the out of scope, being no body to out of scope from. But, no go, cuz it didn't scale. Pointer/ideas welcome. :!: )
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chrisb
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Re: Using named constraint in another constraint in the same sketch

Post by chrisb »

drmacro wrote: Sun Aug 09, 2020 7:34 pm But, then when I use them with Curved Shapes make array I get an out of scope error (I don't think CS arrays like objects from a body...).
This is independent from your constraints naming issue: functions not from PartDesign must not use the features or sketches from inside of the body. They can, however, use expressions to reference things from inside of a body.
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drmacro
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Re: Using named constraint in another constraint in the same sketch

Post by drmacro »

chrisb wrote: Sun Aug 09, 2020 9:02 pm
This is independent from your constraints naming issue: functions not from PartDesign must not use the features or sketches from inside of the body. They can, however, use expressions to reference things from inside of a body.
Yes, I'm fully aware of that, and expected it when I used two sketches and the shapbinder from the body. It is interesting that its happy to complete the CS object, even make it solid or shell, but still throws the error.

I'm experimenting with ways to produce a parametric wing from standard wing .dat files. And, am trying to do it with as few "tricks" as possible. I'm done for the day, but I did start an attempt to use no part design bodies and minimal master sketches as deepSOIC suggested...tomorrow.
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